In increasing performance of a FET, it is known that gate dielectric reliability vs. Tiny scaling is a major industry trade-off. For example, increasing the thickness of a dielectric material stack increases reliability of the semiconductor device, but this increase in stack thickness will also decrease performance. Conversely, decreasing the thickness of a dielectric material stack can decrease reliability of the semiconductor device, but this decrease in stack thickness will also increase performance.
Also, as MOSFET devices are scaled down to less than 100 nanometers in gate or channel length, highly doped, shallow source and drain extension regions can be employed to achieve high drive current capability. The dopants are activated by conducting laser annealing or other millisecond-scale (mSec) annealing of the implanted extension regions either prior, during, or after a more conventional, second-scale Rapid Thermal Anneal (RTA).
Laser annealing can be characterized by the duration of exposure to its radiation. Pulsed lasers, for example, operate in a nanosecond-range regime with exposure durations of tens to two hundreds of nanoseconds with a typical exposure time of less than one hundred nanoseconds. At such short anneals, thermal activation of dopants can be inefficient. Consequently, the dopant activation process relies on a phase transition such as melting-recrystallization of amorphized and doped semiconductors. Due to this reason, nanosecond-scale laser annealing is also referred to as melt laser annealing or pulsed laser annealing. Nanosecond-scale laser annealing also has a very large temperature pattern effect because the laser energy absorbed in surface microstructures does not have sufficient time to spread uniformly within the substrate via thermal diffusion. In addition to large pattern effects, its reliance on inducing phase transitions in microstructures produces substantially different levels of dopant activation near exposure edges or in areas of exposure overlap.
In contrast, millisecond-scale “mSec” laser annealing has exposure times ranging from tens of microseconds to tens of milliseconds. In this range, thermal activation of dopants can be efficient, and the concentration of active dopants is generally proportional to the peak anneal temperature. Continuous wave lasers are employed in this regime. Since the laser beam is shaped in the form of a line, the wafer surface is raster scanned, which means that it is scanned as a pattern of parallel lines or curves. In this case, the exposure time (also referred to as the dwell time) is equal to the characteristic beam width in the scanning direction (often defined at full width at half maximum (FWHM)) divided by the scan speed. The beam length (e.g., about 10 millimeters (mm)) perpendicular to the scanning direction (often defined at full width at 95-99% of the maximum) is usually much smaller than the wafer size (e.g., about 300 mm). As such, adjacent scans (also referred to as exposures) are often applied with some overlap to completely cover the entire wafer surface. In the overlap region, the wafer surface is exposed and annealed twice.